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MC10EP17, MC100EP17 3.3V / 5V ECL Quad Differential Driver/Receiver
The MC10/100EP17 is a 4-bit differential line receiver based on the EP16 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. Inputs of unused gates can be left open and will not affect the operation of the rest of the device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation.
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20 20 1 TSSOP-20 DT SUFFIX CASE 948E XXXX EP17 ALYW 1 20 20 1 SO-20 DW SUFFIX CASE 751D XXXX XXX A L, WL Y, YY W, WW 1 MCXXXEP17 AWLYYWW
* 220 ps Typical Propagation Delay * Maximum Frequency >3.0 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State
* * Safety Clamp on Inputs * Q Output Will Default LOW with Inputs Open or at VEE * VBB Output
= MC10 or 100 = 10 or 100 = Assembly Location = Assembly Lot = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP17DT MC10EP17DTR2 MC100EP17DT MC100EP17DTR2 MC10EP17DW MC10EP17DWR2 MC100EP17DW MC100EP17DWR2 Package TSSOP-20 Shipping 75 Units/Rail
TSSOP-20 2500 Tape & Reel TSSOP-20 75 Units/Rail
TSSOP-20 2500 Tape & Reel SO-20 SO-20 SO-20 SO-20 38 Units/Rail 1000 Tape & Reel 38 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2002
1
September, 2002 - Rev. 4
Publication Order Number: MC10EP17/D
MC10EP17, MC100EP17
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
PIN DESCRIPTION
PIN D[0:3]*, D[0:3]* Q[0:3], Q[0:3] VBB VCC VEE FUNCTION ECL Differential Data Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply
* Pins will default LOW when left open. 1 VCC 2 D0 3 D0 4 D1 5 D1 6 D2 7 D2 8 D3 9 D3 10 VBB
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 100 V > 2 kV Level 1 UL94 V-0 @ 0.125 in 259 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 20 TSSOP 20 TSSOP 20 TSSOP 20 SOIC 20 SOIC 20 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 90 60 30 to 35 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
Thermal Resistance (Junction-to-Case) Wave Solder
2. Maximum Ratings are those values beyond which device damage may occur.
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MC10EP17, MC100EP17
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 42 2165 1365 2090 365 1790 2.0 1890 -40C Typ 50 2290 1490 Max 65 2415 1615 2415 1690 1990 3.3 150 0.5 Min 44 2230 1430 2155 1430 1855 2.0 1955 25C Typ 52 2355 1555 Max 66 2480 1680 2480 1755 2055 3.3 150 0.5 Min 46 2290 1490 2215 1490 1915 2.0 2015 85C Typ 54 2415 1615 Max 68 2540 1740 2540 1815 2115 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 42 3865 3065 3790 3065 3490 2.0 3590 -40C Typ 50 3990 3190 Max 65 4115 3315 4115 3390 3690 5.0 150 0.5 Min 44 3930 3130 3855 3130 3555 2.0 3655 25C Typ 52 4055 3255 Max 66 4180 3380 4180 3455 3755 5.0 150 0.5 Min 46 3990 3190 3915 3190 3615 2.0 3715 85C Typ 54 4115 3315 Max 68 4240 3440 4240 3515 3815 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 W to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 11) Input HIGH Current Input LOW Current 0.5 Min 42 -1135 -1935 -1210 -1935 -1510 -1410 VEE+2.0 -40C Typ 50 -1010 -1810 Max 65 -885 -1685 -885 -1610 -1310 0.0 150 0.5 Min 44 -1070 -1870 -1145 -1870 -1445 -1345 VEE+2.0 25C Typ 52 -945 -1745 Max 66 -820 -1620 -820 -1545 -1245 0.0 150 0.5 Min 46 -1010 -1810 -1085 -1810 -1385 -1285 VEE+2.0 85C Typ 54 -885 -1685 Max 68 -760 -1560 -760 -1485 -1185 0.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP17, MC100EP17
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 14) Input HIGH Current Input LOW Current 0.5 Min 47 2155 1355 2075 1355 1775 2.0 1875 -40C Typ 55 2280 1480 Max 63 2405 1605 2420 1675 1975 3.3 150 0.5 Min 50 2155 1355 2075 1355 1775 2.0 1875 25C Typ 58 2280 1480 Max 66 2405 1605 2420 1675 1975 3.3 150 0.5 Min 54 2155 1355 2075 1355 1775 2.0 1875 85C Typ 62 2280 1480 Max 70 2405 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 W to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH Characteristic Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 17) Input HIGH Current Min 47 3855 3055 3775 3055 3475 2.0 3575 -40C Typ 55 3980 3180 Max 63 4105 3305 4120 3375 3675 5.0 150 Min 50 3855 3055 3775 3055 3475 2.0 3575 25C Typ 58 3980 3180 Max 66 4105 3305 4120 3375 3675 5.0 150 Min 54 3855 3055 3775 3055 3475 2.0 3575 85C Typ 62 3980 3180 Max 70 4105 3305 4120 3375 3675 5.0 150 Unit mA mV mV mV mV mV V mA
IIL Input LOW Current 0.5 0.5 0.5 mA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 W to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH Characteristic Power Supply Current Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 20) Input HIGH Current Min 47 -1145 -1945 -1225 -1945 -1525 -1425 VEE+2.0 -40C Typ 55 -1020 -1820 Max 63 -895 -1695 -880 -1625 -1325 0.0 150 Min 50 -1145 -1945 -1225 -1945 -1525 -1425 VEE+2.0 25C Typ 58 -1020 -1820 Max 66 -895 -1695 -880 -1625 -1325 0.0 150 Min 54 -1145 -1945 -1225 -1945 -1525 -1425 VEE+2.0 85C Typ 62 -1020 -1820 Max 70 -895 -1695 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V mA
IIL Input LOW Current 0.5 0.5 0.5 mA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 W to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP17, MC100EP17
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40C Symbol fmax tPLH, tPHL tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 2 Fmax/JITTER) Propagation Delay to Output Differential 10 Series 100 Series Cycle-to-Cycle Jitter (See Figure 2 Fmax/JITTER) Input Voltage Swing (Differential) Output Rise/Fall Times (20% - 80%) Q, Q 150 100 125 150 Min Typ >3 Max Min 25C Typ >3 Max Min 85C Typ >3 Max Unit GHz ps 200 220 .2 800 160 275 300 <1 1200 220 150 100 150 180 220 250 .2 800 170 300 320 <1 1200 230 150 120 200 200 260 290 .2 800 190 350 360 <1 1200 250 ps mV ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V.
800 700 VOUTpp (mV) 600 500 400 300 200 100 0
8 7 6 5 4 3 2 1 (JITTER) 3000 4000 5000 6000 JITTEROUT ps (RMS)
0
1000
2000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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EE EE
EEEEEEEE EEEEEEEE EEEEEEEE
MC10EP17, MC100EP17
Q Driver Device Q 50 W 50 W
D Receiver Device D
V TT V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC10EP17, MC100EP17
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SO-20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D A
11 X 45 _
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
18X
e
A1
T
C
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L
IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E q
L/2
20
11
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. ICONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
MC10EP17, MC100EP17
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC10EP17/D

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